The invention relates generally to ATM systems and, more particularly, to ATM systems that handle both variable and constant bit rate traffic.
Constant bit rate (CBR) traffic is generally processed in accordance with ATM adaptation layer (AAL) 1 by an AAL1 segmentation and reassembly processor (SAR) into an essentially steady stream of ATM cells. Variable bit rate (VBR) traffic, which is bursty in nature, is typically processed into ATM cells in accordance with AAL5 by an AAL5 SAR.
The SARs, which are included in a router, essentially schedule the cells in virtual circuits for transport to the physical layer over the router""s internal xe2x80x9cUTOPIAxe2x80x9d bus. The physical layer then forwards the cell traffic over a WAN connection to an ATM switch, which includes a xe2x80x9cpolicerxe2x80x9d that controls the flow of traffic to the ATM network. The policer operates in accordance with a known generic cell rate algorithm (GCRA) that determines for each virtual circuit a minimum time between cells. For a CBR virtual circuit, the traffic parameters typically applied to the GCRA are cell delay variation tolerance (CDVT) and peak cell rate. For a VBR virtual circuit, the parameters typically applied to the GCRA are a sustainable cell rate and maximum burst size. The policer forwards to the ATM network those cells that meet the minimum time between cells associated with the virtual circuit, and discards the cells that do not. For a more detailed discussion of traffic flow parameters refer to Ginsberg, David, ATM Solutions for Enterprise Internetworking, Addison-Wesley, 1996.
The CBR traffic typically originates from time-division-multiplexed (TDM) lines, and the framing of the TDM lines basically controls the timing of the generation of the associated AAL1 CBR cells. The cells are thus produced with very little cell delay variation. The AAL1 SAR processor provides the CBR cells to the UTOPIA bus as soon as the cells are generated, nearly preserving the inherent constant timing between the cells. In contrast, the AAL5 VBR cells are produced and sent over the UTOPIA bus in bursts, in accordance with applicable sustainable cell rate and maximum burst size parameters.
Some systems require that all traffic from a given user or set of users travel over a single virtual path that conforms, as an aggregate, to one peak cell rate and CDVT.
A known prior system that produces a traffic stream that conforms to the aggregate parameters includes, in addition to the AAL1 SAR and the AAL5 SAR, a third processor that acts as a xe2x80x9cmasterxe2x80x9d scheduler. The master scheduler processor receives and buffers all of the AAL5 data cells and the AAL1 CBR cells into associated queues based on the virtual paths, and reschedules the queued cells to conform to the aggregate traffic parameters. While the master scheduler works well, it requires extensive buffering and adds considerable complexity to the system.
The invention is a system and a method of operating the system in which VBR data traffic and CBR traffic that are produced by different SARs are scheduled on the same virtual paths by including in an AAL5 data cell stream strategically placed xe2x80x9cCBR opportunity cells.xe2x80x9d Each CBR opportunity cell is associated with a virtual path, and operates essentially as a placeholder for the insertion of a conventional AAL1 CBR cell that is directed to the same virtual path. An add/drop multiplexer, which receives both AAL1 CBR cells produced by a conventional AAL1 SAR and the AAL5 data cell stream with the included CBR opportunity cells, replaces the CBR opportunity cells with the appropriate AAL1 CBR cells, and provides the stream of AAL5 and AAL1 cells to the physical layer.
More specifically, a scheduler that is included in an AAL5 SAR processor controls the timing of the generation of conventional AAL5 data cells that include in their payloads the traffic received from various data sources and, also, the timing of the periodic generation of the CBR opportunity cells from locally-stored xe2x80x9cdummy data.xe2x80x9d Since the CBR opportunity cells are placeholders for the AAL1 CBR cells, the scheduler completely controls the timing of both the CBR cells and the AAL5 data cells for each virtual path. The scheduler thus schedules the cells to meet the aggregate peak cell rate and CDVT associated with the respective virtual paths.
At the same time, the AAL1 SAR produces the AAL1 CBR cells in a conventional manner and provides the cells, as they are produced, to the add/drop multiplexer, which queues the cells by virtual paths. When the multiplexer receives a CBR opportunity cell, the multiplexer replaces the cell with the first CBR cell in the queue that corresponds to the virtual path with which the CBR opportunity cell is associated. If there are no cells queued for the virtual path, the multiplexer blocks the CBR opportunity cell from passing to the physical layer, and the physical layer fills in the gap that results with an idle cell.
To maintain the inherent timing of the AAL1 cells, the scheduler schedules the CBR opportunity cells at rates that slightly exceed the maximum rate at which the associated AAL1 cells are produced. The queues of AAL1 CBR cells are thus kept relatively short, preventing overflow.